This article is from WeChat official account:Semiconductor Industry Observation (ID: icbank) , author: Chang Qiu, original title: “1nm Tough Battle Started”, title picture from: Visual China
At present, even though Moore’s Law has some failures, the process technology is still moving forward in an orderly manner. The 5nm node process has been mass-produced, and TSMC’s 3nm is about to achieve risky trial production, and plans to achieve mass production in 2022, and the company’s 2nm process has also been scheduled for trial production and mass production. The next step is to conquer the 1nm process node, but from the current situation, the research and development of 1nm is not yet mature, and there are still many uncertain factors. Therefore, when its trial production and mass production will be on the agenda, it still needs the industry Work together.
Advanced process technology(here refers to nodes below 10nm)Compared to more mature processes, various factors related to chip manufacturing are brand new , Is also quite challenging. Generally speaking, if you want to mass produce usable advanced process chips,Especially for 3nm, 2nm and 1nm, the manufacturing process and manufacturing equipment have become the most challenging factors. Among them, the manufacturing process can be roughly divided into transistor architecture and materials, and the core element of the manufacturing equipment is the EUV lithography machine. . These are all top technologies, especially for 1nm. These technologies are still in the research stage and are not mature yet. Only by solving them, can the mass production of the 1nm process really be put on the agenda.
1. Transistor architecture
At present, TSMC and Samsung have achieved mass production of 7nm and 5nm processes, and the corresponding transistors still use FinFET architecture. With the evolution to 3nm and 2nm, FinFET has been unable to meet the demand, gate-all- around(GAA)< span class="text-remarks" label="Remarks">architecture came into being, which is also called nanosheet, and the 1nm process puts forward higher requirements for transistor architecture. In order to extend the scalability of nanosheet devices to the 1nm node, the European research organization IMEC proposed an architecture called forksheet. In this architecture, the sheet is controlled by a fork-shaped gate structure, which is implemented by introducing a dielectric layer between the pMOS and nMOS devices before the gate is patterned. This dielectric layer physically separates the p-gate trench from the n-gate trench, making the n-to-p pitch tighter than FinFET or nanosheet devices. Through simulation, IMEC predicts that forksheet has ideal area and performance scaling, as well as lower parasitic capacitance.
In addition, 3D “complementary FET” (CFET) is also a transistor solution for the 1nm process. A notable feature of CFET technology is its strong similarity with the nanosheet topology. The novelty of CFET lies in the vertical placement of pFET and nFET nanosheets. The CFET topology takes advantage of typical CMOS logic applications, where a common input signal is applied to the gates of nFET and pFET devices.
The processing of CFET devices requires special attention to the formation of pFET and nFET. The epitaxial growth of SiGe for pFET source/drain is used to introduce compressive strain in the channel to improve hole mobility. Then pFET gate oxide and metal gate deposition are performed. Subsequently, the epitaxial Si growth of the nFET source/drain nodes, the subsequent gate oxide and metal gate deposition must comply with the material chemical constraints imposed by existing pFET devices.
At VLSI 2020, IMEC demonstrated the first experimental proof of concept of a CFET device, which is manufactured in a monolithic process. The team managed to overcome the key process challenge of this complex process scheme, which is to process the CFET from the bottom to the top starting from the substrate. In CFET, the bottom device (such as pFET) is processed, and then wafer bonding is performed to form the top device(such as nFET) channel, and then further process the top device. CFET provides a more flexible choice for the channel material used in the top device.
In addition to IMEC and TSMC, relevant research institutions in mainland China are also conducting research on 1nm transistors and have achieved certain results.
For example, in April this year, Professor Liu Yuan’s team from the School of Physics and Microelectronics of Hunan University successfully realized a 1nm physical channel length vertical field effect transistor by using van der Waals metal integration. It provides new ideas for the further improvement of the performance of semiconductor devices. The physical channel length of a transistor refers to the distance between the source and drain in the transistor. The physical channel length is a key performance indicator of the transistor: the shorter the channel length, the better the performance.
Compared with traditional metal deposition technology, van der Waals metal integration can achieve an atomic level flat interface, thereby ensuring the nearly perfect flatness of the ultra-thin atomic channel, thereby minimizing the occurrence of leakage current. Therefore, devices with van der Waals metal electrodes have greatly improved gate control and switching ratios.high.
Professor Yuan Liu’s team found that a vertical transistor with a channel length of 5nm exhibited an on-off ratio of three orders of magnitude, which was more than an order of magnitude higher than that of conventional vapor-deposited electrode devices. By reducing the channel length to 0.65nm, the switching ratio of the single-layer device has decreased, but the van der Waals vertical transistor still exhibits the intrinsic N-type semiconductor characteristics, indicating that the short channel effect is still not dominant at the atomic scale. The performance of the device. Although the device exhibits a certain tunneling current and short channel effect in the single-layer limit, they still confirm that van der Waals metal electrodes can realize sub-1nm vertical transistors with device functions.
In addition, the research team of the Institute of Physics, Chinese Academy of Sciences has constructed transistor devices with a size of less than 1nm and composed of single molecules It uses a controllable ablation electrode method to construct a nano-metal electrode pair, in which a single manganese phthalocyanine molecule is embedded, and the gate electrode electrostatically regulates the energy of multiple molecular orbitals. The second-order Kondo effect is reported in the experiment for the first time. The evolution method verifies the linear relationship predicted in the calculation method of the digital renormalization group.
II. Materials
In the manufacturing process of advanced process chips, the previous process is responsible for manufacturing transistors of the corresponding structure, while the intermediate process and the subsequent process are to connect these independent transistors to achieve the corresponding chip functions and performance. Need to use a variety of semiconductor materials.
As mentioned above, the 1nm process requires forksheet and CFET transistor architectures. These architectures put forward new requirements for local interconnection. Accordingly, the subsequent process needs Use new materials, such as ruthenium(Ru), molybdenum(Mo) and metal alloys, it is also necessary to reduce the contact resistance of the intermediate process.
For the later process, the resistance and capacitance of metal lines and vias are still the most critical parameters. One way to solve this problem is to use another metallization structure called “zero through hole mixing height.” This solution can flexibly change the resistance to the capacitor according to the application requirements of the metal wire.
For the intermediate process, in order to further alleviate wiring congestion and meet the requirements of the newly proposed transistor structure, this process requires further innovation. For example, in CFETs, there is a need to provide a new solution for contacting the gate, which is now common for nFET and pFET devices. In addition, high-aspect-ratio through holes interconnect various components, which have now been expanded to three dimensions. However, the main parasitic resistance of these deep vias needs to be reduced. This can be achieved by introducing advanced contacts, such as the use of ruthenium.
Recently, TSMC has achieved a result in cooperation with National Taiwan University and Massachusetts Institute of Technology (MIT) , Found that two-dimensional material combined with semi-metal bismuth (Bi) can achieve extremely low resistance, close to the quantum limit, and can meet the needs of 1nm process .
In the past, semiconductors used three-dimensional materials, but this time they use two-dimensional materials. The thickness can be less than 1nm(the thickness of 1~3 layers of atoms) , Which is closer to the limit of the thickness of solid semiconductor materials. The material properties of semi-metallic bismuth can eliminate the energy barrier to the two-dimensional semiconductor, and when the semi-metallic bismuth is deposited, it will not destroy the atomic structure of the two-dimensional material.
The 1nm process passes through two-dimensional materials with only 1~3 layers of atomic thickness, and the electrons go from the source (source) to molybdenum disulfide. It is the electron channel layer of the material, with a gate (gate) to control the voltage, and then from the drain (drain) flows out, using bismuth as the material of the contact electrode can greatly reduce the resistance and increase the transmission current, making the two-dimensional material a new type of semiconductor material that can replace silicon.
3. Manufacturing equipment
1nm